Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the next years, the well-known synchronous design style will not be able to keep pace with the increase of speed and capabilities of integration of advanced processes. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs. This paper will present test strategies for 2-phase asynchronous-synchronous, and vice versa, interfaces. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all the stuck-at-faults within the asynchronous-synchronous interfaces.